The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventors hereof, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted to be prior art against the present disclosure.
Locking loop circuits include phase-locked loops (PLLs) and delay-locked loops (DLLs). Both types of locking loop circuits use some type of error detector to determine phase error and/or frequency error in the output signal to adjust the loop to correct the error. For example, many digital phase-locked loops (DPLLs) employ a phase-error detector, such as a Bang-Bang phase detector, that merely indicates whether the phase needs to be advanced or retarded.
However, such DPLLs require relatively long locking times. For applications requiring short (i.e., fast) locking times, a phase-error detector that provides a quantized indication of phase error, with good resolution, is needed.
However, such a phase-error detector, which may be implemented as a time-to-digital converter (TDC), would need to be wide—i.e., encompass a large number of bits. A TDC may be implemented as a delay chain, with one inverter per bit. Each inverter would need its own ancillary circuitry, including power, clocks, etc. Therefore, there could be substantial area and power penalties to provide a wide TDC.